Complementary metal-oxide-semiconductor (CMOS) devices often require isolation between adjacent arrays of transistors. In fin field effect transistor (finFET) technology, this may be accomplished by placing one or more dummy gates between adjacent fin arrays to form what is known as a “diffusion break.” Diffusion breaks may take various forms.
In a double diffusion break (DDB), a single fin is cut, prior to gate patterning, to form two adjacent fin arrays having a gap in between. A dummy gate is formed on each side of the gap (i.e., on the gap-end of each fin array). This approach thus decouples fin patterning from gate formation and allows the dummy gates to be processed in a manner similar to the active gates.
In a single diffusion break (SDB), a single fin is cut, after gate patterning, to form two adjacent fin arrays having a gap in between. A single dummy gate is formed in the gap between the fin arrays. The reduction in the number of dummy gates formed in the gap (i.e., from two to one), relative to a DDB, allows for a denser circuit to be fabricated (as less space is consumed by dummy devices).